Multiplication, Division and Floating Point Arithmetic

See accompanying powerpoint presentations for illustrations of integer multiplication and divide and IEEE floating point format standards.

Floating Point Addition

Consider the addition of two floating point numbers

21.44 + 7.24

Step 0. Convert both numbers to binary

21.44 = 10101.01110000101 = 1.010101110000101 E+4

7.24 = 111.0011110101110 = 1.110011110101110 E+2

Adding the bias, these exponents become

4 + 127 = 131 = 10000011

2 + 127 = 129 = 10000001

The numbers are stored according to the IEEE floating point standard. The first significant bit is always a 1 and is not stored as part of the significand.

Step 1. Compare exponents

The exponents of the two registers are subtracted. The difference is positive, indicating that the exponent in register A (on the left is larger. Control selects the exponent from register A (by asserting 0 at the multiplexer on the left) to pass to the next section of the adder to be used as the preliminary result for the exponent. The difference between the two exponent is 2, indicating the significand in register B must be shifted right two places. Before entering the ALU or the shift register, the 23-bit significands are expanded to 32 bits by inserting the leading implicit 1 and filling in leading 0's. (To provide for roundoff, trailing 0's may also be appended to the original 23 bits.)

Control selects the (expanded) contents of register B to be placed in the shift register and the contents of register A (expanded) to be sent directly to the ALU. The contents of register B are shifted right two places and the two terms are added.

In this example, the 23 bits of the significand are mapped into bits 24 -- 2 during the process of expanding to 32 bits. Bits 0 and 1 are set to 0 initially and used for calculating roundoff. The implicit leading 1 is set in bit 25 and bits 26 -- 31 hold leading 0's. The input to the ALU (after shifting) is shown in the diagram below. (Note! Since the last two bits of the significand in register B are both 0, shifting right just moves these two 0's into the additional trailing bits.)

Since there was no carry into bit 26 during the add, there is no need to renormalize the result, and since the value in the last two roundoff bits is 00, the result does not have to be rounded off. The result stored in the mantissa (significand) is bits 24 through 2 of the 32-bit result. The leading 1 in bit 25 is again implicit.

The two multiplexers in this portion of the adder select between the exponent and result from the adder and the exponent and result after any incrementing/decrementing and shifting and rounding has occurred. In the first pass, the multiplexers will always be set (to 0) to select the exponent and result that have been supplied by the earlier steps in the process. In some cases, after rounding has occurred the result will have to be normalized again and both multiplexers will have their control set to 1 to accept the exponent and result as they have been modified.

Multiplication of floating point numbers

The algorithm for multiplying two floating-point numbers is illustrated below:

This algorithm is best illustrated with an example.

Multiply 21.44 by 7.24

Again, start by converting both of these numbers to binary floating point numbers in IEEE format.

The leading 1 bit is implicit in this representation.

Step 1. Add the biased exponents (subtracting the bias)

In decimal we are performing the following addition 131 + 129 - 127 = 133 = 10000101

Step 2. Multiply the significands

Copy the two significands into 32-bit registers and form the product in a 64-bit register using

the multiplication algorithm described in the accompanying powerpoint presentation.

Just keeping the first 4 bits of the two significands (with the implicit 1's restored) we have

the following product (shown step-by-step)

Place the multiplier in the rightmost 4 bits of the 8-bit product register.

Shift 1 -- The bit shifted out of the product register is 0. No add is performed.

Shift 2 -- The bit shifted out of the product register is 1. Add the multiplicand to the first 4 bits of the product register.

Shift 3 -- Again add the multiplicand to the leftmost 4 bits of the product register.

Shift 4 -- Shift then add.

Finally, shift right and end. The product is found in the 8-bit product register (140)

Step 3. Normalize the product shifting (right) if necessary.

The product of the two numbers (4-bit) numbers now is:

Remember! The 8-bit product register is a simplification of a 64-bit floating point register. The product must be stored in a 32-bit register (of which only 24 bits are significant). The product must be shifted right 4 times. After each shift right, the exponent is incremented and checked that overflow has not occurred (that there is no carry out of the 8^th bit).

After the product has been shifted (right) the requisite number of times, the portion of the product that is shifted into the last 8 unused bits of the 32-bit second word of the product register are tested to see if they are greater than or equal to 1 0 0 0 0 0 0 0. If so, the value in the upper 24 bits of this register is incremented and a test is made that the result is still normalized after round off has occurred.

MIPS Floating Point Instructions

MIPS has two floating point instruction formats.

FR Instructions include:

Floating point arithmetic instructions.

add.s, add.d, sub.s, sub.d, mul.s, mul.d, div.s, div.d

Floating point compares: c.eq.s, c.eq.d, c.lt.s, c.lt.d, c.le.s, c.le.d

FI has two instructions:

bc1t branch if floating point condition is true

bc1f branch if floating point condition is false