SPARC Registers

Risc microprocessors are typically designed to have a relatively small number of instructions that can be decoded and run quickly. To enable the instructions to run quickly, the number of memory accesses is kept to the smallest amount possible. To help limit the number of memory accesses, RISC machines typically have a large number of registers. Both the MIPS and the SPARC machines have a relatively large number of registers for the programmer/compiler to use. In the MIPS machine, there are 32 registers that the program can use (actually, only 24 of the 32 are generally available). In the SPARC machine there are 32 registers that the program can use AT ONE TIME (actually, 28 of the 32 are generally available). Since the SPARC has been optimized for subroutine calls, the actual number of registers in the microprocessor is much larger than 32 (often 124 registers exist), but only 32 registers are visible to the program at any given time (see the subroutine overview section for more information).

Registers can be categorized by function since they are typically created for a given purpose. On RISC machines, if the register is not being used for the purpose it is designed for, it is available to use by any instruction.

The most general registers are the "temporary" registers. These registers exist to store values loaded from memory or calculated by the ALU before being stored in memory. These registers are not preserved across subroutine calls. Basically, the program should use these as the "general use" registers for the program. The MIPS machine has ten temporary registers which are designated as $t0-$t9 (registers 8-15,24, and 25). The SPARC machine has only eight temporary registers designated %l0-%l7 (registers 16-23), but the SPARC often has other registers available that can also be used as temporaries if the program needs them.

For memory accessing and for subroutine calls, both the MIPS and the SPARC provide a few specialized registers. Since they are key to the operation of the machine, the program should use the registers as designed, unless they are known to not be needed. The MIPS and the SPARC both provide a stack pointer register, $sp and %sp. They also both provide a frame pointer register, $fp and %fp. The MIPS machine reserves register $at for the assembler and $k0 and $k1 for the OS kernel. The MIPS machine also has a global memory pointer, %gp, that the SPARC doesn't have. In other words, the MIPS machine reserves four registers that the program can't generally use. The SPARC does not have this limitation.

Although the SPARC has more branch instructions than the MIPS, often the comparisons still need to be made against the constant zero. Consequently, both the MIPS and the SPARC reserve one register for the constant zero. This register, designated $zero on MIPS and %g0 on SPARC, will always return zero when read from and will not change if written to.

To provide for subroutines, there needs to be registers available for passing the arguments to the registers, returning values from the registers and returning from the subroutine.

The MIPS machine has four function argument registers, designated $a0-$a3, two return value registers, designated $v0-$v1, and one register for the return address, designated $ra. The SPARC machine has six registers for function arguments, designated %i0-%i5, six registers for function return values, designated %o0-%o5, and a function return address, designated %i7.

The SPARC machine has seven registers that are not present on the MIPS machine called %g1-%g7 (recall that %g0 is the zero register). These registers are "global" registers and their value does not change across subroutine calls. Actually, all subroutines use the same global registers; therefore the SPARC machine doesn't need the global register pointer that the MIP machine has. If the SPARC needs more globals, it can use the general memory.

In both machines, if doing a subroutine call requires more arguments than the machine provides registers for, than the program must use the stack to save the additional information.

Since the SPARC machine has more registers available to the program at any given instant and since the machine has some optimazation for subroutine calls, the SPARC machine has a clear advantage over the MIPS machine for register design.

The layout of the SPARC registers is:

SPARC Register Layout

Direct Register Comparison

Like the MIPS processor, the SPARC has a large number of registers. Many of these registers are similar to the MIPS registers. Like the MIPS, there are thirty-two registers available to the compiler/programmer to use. The layout of the registers is shown below.

Paul Austin Charles Gates